#ifndef _TABLES_TRANS_CTL_H
#define _TABLES_TRANS_CTL_H
/*
 * Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
 * This fork is protected by the GNU affero GPLv3 with additionnal rights
 * Original code from Advanced Micro Devices, Inc.
 */

#define TRANS_ACTION_DISABLE		0
#define TRANS_ACTION_ENA		1
#define TRANS_ACTION_LCD_BLOFF		2
#define TRANS_ACTION_LCD_BLON		3
#define TRANS_ACTION_BL_BRIGHTNESS_CTL	4
#define TRANS_ACTION_LCD_SELFTEST_START	5
#define TRANS_ACTION_LCD_SELFTEST_STOP	6
#define TRANS_ACTION_INIT		7
#define TRANS_ACTION_DISABLE_OUTPUT	8
#define TRANS_ACTION_ENA_OUTPUT		9
#define TRANS_ACTION_SETUP		10
#define TRANS_ACTION_SETUP_VSEMPH	11
#define TRANS_ACTION_PWR_ON		12
#define TRANS_ACTION_PWR_OFF		13

#define TRANS_CFG_SEL_MASK		0xc0
#define TRANS_CFG_SEL_SHIFT		6
#define TRANS_CFG_CLK_SRC_MASK		0x20
#define TRANS_CFG_CLK_SRC_SHIFT		4
#define TRANS_CFG_ENC_SEL_BIT		3
#define TRANS_CFG_LINK_SEL_BIT		2
#define TRANS_CFG_COHERENT_MODE_BIT	1
#define TRANS_CFG_DUAL_LINK_CON_BIT	0

struct vs_pre_emph {
	u8 lane_sel;
	u8 lane_set;
} __packed;

struct trans_ctl_params {
	union {
		__le16 pixel_clk;	/* in 10kHz unit */
		__le16 init_info;	/* when init uniphy, lower 8bit is used
					   for connector type defined as an
					   object id */
		struct vs_pre_emph mode;/* dp voltage swing/pre-emphasis mode */
	} __packed;
	u8 cfg;				/* [7:6] transmitter selection
					     0: transmitter 1 (uniphy AB)
					     1: transmitter 2 (uniphy CD)
					     2: transmitter 3 (uniphy EF)
					   [5:4] clock source reference
					     0: pll1
					     1: pll2
					     2: external clock
					   [3] encoder selection
					     0: data/clock for encoders A/C/E
					     1: data/clock for encoders B/D/F
					   [2] link selection
					     0: uniphy link A/C/E (primary) when
					        dual link connector bit is 0
						or
						master link is A/C/E when
						dual link connector bit is 1
					     1: uniphy link B/D/F (secondary)
					        when dual link connector bit is
					        0
						or
						master link is B/D/F when
						dual link connector mit is 1
					   [1]
					     1:coherent mode (DVI/HDMI)
					   [0]
					     1:dual link dvi connector */


	u8 action;			/* define as TRANS_ACTION_XXX */
	u8 lanes_n;
	u8 rsvd[3];
} __packed;
#endif
